A sense amplifier comprising: a first differential amplifier including a first input, a second input, a first output and a first voltage offset wherein said first input is coupled to a memory cell via a first capacitive element wherein said second input is coupled to ground via a second capacitive element wherein said first output of said differential amplifier is coupled to a comparator via a second differential amplifier including a third input, a fourth input, a second output and a second voltage offset said memory cell including a read state, a write state and a data state and read/write circuitry coupled to said memory cell and capable of reading or writing said data state of said memory cell wherein said read/write circuitry further comprises: a sense data phase wherein said read/write circuitry reads said data state a write reference phase wherein said read/write circuitry writes said data state to a first reference state and a second reference state and a sense reference phase wherein said read/write circuitry reads said second reference state wherein said first differential amplifier senses said data state by sensing a first difference between said first input and said second input, canceling said first voltage offset and amplifying said first difference wherein said first differential amplifier senses a second difference between said data state and said second reference state to thereby determine a polarity of said data state wherein said third input is coupled to said first output of said first differential amplifier, and said fourth input is coupled to said second output of said first differential amplifier wherein said third input is coupled to said first output of said first differential amplifier via said second capacitive element wherein said fourth input is coupled to said second output of said first differential amplifier via a third capacitive element and wherein said second differential amplifier cancels said second offset voltage and further amplifies said second difference.Ģ. Method and apparatus for sensing the state of floating gate memory cells by applying a variable gate voltageġ. Reference potential for sensing data in electronic storage element Sense amplifier for non-volatile memory devices Magnetic random access memory (MRAM) device including differential sense amplifiers Interconnection network for connecting memory cells to sense amplifiers Magneto-resistive memory having sense amplifier with offset controlĬonfiguration for self-referencing ferroelectric memory cells Sense amplifier for a memory having at least two distinct resistance states Magnetic memory sensing method and apparatus Method and system for performing readout utilizing a self reference schemeĬapacitively coupled sensing apparatus and method for cross point magnetic random access memory devices Offset compensated sensing for magnetic random access memory Noise resistant small signal sensing circuit for a memory device Method and apparatus for current sense amplifier calibration in MRAM devices Sense amplifier for low voltage high speed sensing Method and apparatus for sensing flash memory using delta sigma modulation Semiconductor Memory Device and Method of Reading Data Therefrom Spin transfer MRAM device with reduced coefficient of MTJ resistance variation Leakage compensation during program and read operations Method and system for providing a sense amplifier and drive circuit for spin transfer torque magnetic random access memory
Sense amplifier circuitry for integrated circuit having memory cell array, and method of operating same Spin-transfer torque memory self-reference read method Non-volatile semiconductor memory device that changes a load capacitance of a sense node in accordance with a logic value of read information System and Methods Using a Multiplexed Reference for Sense Amplifiers
Resistive memory devices and related methods
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